Sonoff NSPanel Pro 120: Linux Display Subsystem [Part 2]
![Sonoff NSPanel Pro 120: Linux Display Subsystem [Part 2]](/content/images/size/w1200/2025/02/wayland-screenshot-2025-02-20_11-09-58-1.png)
In the previous article, we found out what the DSS (Display Subsystem) consists of and its terminology. We also have a .dts reference file from the factory firmware, so we are ready to define our peripheral in the DTS and finally make the screen work.
Let’s create a new .dts file for our panel under kernel/arch/arm64/boot/dts/rockchip and name it sonoff_nspanel_120_pro.dts. The starting contents would be as follows:
/dts-v1/;
#include "px30.dtsi"
#include "rk3326-linux.dtsi"
#include "px30-evb-ddr3-v10.dtsi"
/ {
model = "The RoboVerse Sonoff NSPanel 120 Pro";
compatible = "rockchip,sonoff_nspanel_120_pro", "rockchip,px30";
/delete-node/ test-power;
};The DTS tree definition is flexible and multilayered. We can include lower-level DTS files and modify or create nodes at the upper level. To make the SDK pick up our DTS, we should add RK_KERNEL_DTS_NAME="sonoff_nspanel_120_pro" to our SDK configuration file located at device/rockchip/rk3326/sonoff_nspanel_pro_120_defconfig.
So, as a recap, the chain that we should follow: DSS → CRTC (VOP) → Encoder → Connector → Panel .
The DSS definition would be as follows:
&display_subsystem {
status = "okay";
logo-memory-region = <&drm_logo>;
route {
route_lvds: route-lvds {
status = "disabled";
logo,uboot = "logo.bmp";
logo,kernel = "logo_kernel.bmp";
logo,mode = "center";
charge_logo,mode = "center";
connect = <&vopb_out_lvds>;
};
route_dsi: route-dsi {
status = "okay";
logo,uboot = "logo.bmp";
logo,kernel = "logo_kernel.bmp";
logo,mode = "center";
charge_logo,mode = "center";
connect = <&vopb_out_dsi>;
};
route_rgb: route-rgb {
status = "disabled";
logo,uboot = "logo.bmp";
logo,kernel = "logo_kernel.bmp";
logo,mode = "center";
charge_logo,mode = "center";
connect = <&vopb_out_rgb>;
};
};
};We can see that display_subsystem and route_dsi are being enabled, and then they are chained with vopb_out_dsi. So, next, let’s move on to the VOP configuration. The RK3326 has two VOPs (vop_big and vop_little), which means that two screens can be connected simultaneously (similar to a regular PC setup with dual monitors). However, I won’t go into the details here. For our purposes, we are using VOP1 (vop_big). The CRTC(VOP) node looks as follows:
vopb: vop@ff460000 {
compatible = "rockchip,px30-vop-big";
reg = <0x0 0xff460000 0x0 0x260>, <0x0 0xff460a00 0x0 0x400>;
rockchip,grf = <&grf>;
reg-names = "regs", "gamma_lut";
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>,
<&cru HCLK_VOPB>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>;
reset-names = "axi", "ahb", "dclk";
iommus = <&vopb_mmu>;
power-domains = <&power PX30_PD_VO>;
status = "okay";
vopb_out: port {
#address-cells = <1>;
#size-cells = <0>;
vopb_out_dsi: endpoint@0 {
reg = <0>;
remote-endpoint = <&dsi_in_vopb>;
};
vopb_out_lvds: endpoint@1 {
reg = <1>;
remote-endpoint = <&lvds_vopb_in>;
};
vopb_out_rgb: endpoint@2 {
reg = <2>;
remote-endpoint = <&rgb_in_vopb>;
};
};
};
vopb_mmu: iommu@ff460f00 {
compatible = "rockchip,iommu";
reg = <0x0 0xff460f00 0x0 0x100>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vopb_mmu";
clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
clock-names = "aclk", "iface";
power-domains = <&power PX30_PD_VO>;
#iommu-cells = <0>;
rockchip,disable-device-link-resume;
status = "okay";
};Here are a few comments: vopb_mmu is a DMA mechanism used to fetch data from the framebuffer allocated in the RAM. We can see that the chain proceeds through endpoint@0 to dsi_in_vopb.
The encoder in our case is the &dsi node, as it converts the output of the VOP into a format that our display can understand. It looks as follows:
dsi: dsi@ff450000 {
compatible = "rockchip,px30-mipi-dsi";
reg = <0x0 0xff450000 0x0 0x10000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_MIPI_DSI>;
clock-names = "pclk";
phys = <&video_phy>;
phy-names = "dphy";
power-domains = <&power PX30_PD_VO>;
resets = <&cru SRST_MIPIDSI_HOST_P>;
reset-names = "apb";
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
dsi_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_dsi>;
};
dsi_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_dsi>;
};
};
};
};As we can see, the nodes cross-reference each other using labels (dsi_in_vopb points to vopb_out_dsi and vice versa). Additionally, in the RK3326, as we see in the line phys = <&video_phy>, the &dsi node uses a hardware PHY for its operation. Its node looks as follows:
video_phy: dsi_dphy: phy@ff2e0000 {
compatible = "rockchip,px30-dsi-dphy", "rockchip,px30-video-phy";
reg = <0x0 0xff2e0000 0x0 0x10000>,
<0x0 0xff450000 0x0 0x10000>;
reg-names = "phy", "host";
clocks = <&pmucru SCLK_MIPIDSIPHY_REF>,
<&cru PCLK_MIPIDSIPHY>, <&cru PCLK_MIPI_DSI>;
clock-names = "ref", "pclk", "pclk_host";
resets = <&cru SRST_MIPIDSIPHY_P>;
reset-names = "apb";
#phy-cells = <0>;
power-domains = <&power PX30_PD_VO>;
status = "okay";
};The next step is to define the connector and panel. In our case, the connector and panel are defined as a single node. This node will specify the physical characteristics of the panel, including its timings, resolution, and initialization sequence.
I obtained 99% of these parameters from the extracted .dts file from the factory firmware. So far, I haven’t been able to identify the manufacturer or model of the display. It seems that the MIPI DSI association is a closed group, and you need to be a manufacturer and pay a significant amount to gain access.
Nevertheless, it appears that all MIPI DSI-compatible displays require a certain set of parameters and initialization sequences. To be honest, without having the datasheet or .dts, it’s probably best not to waste time on it.
&dsi {
panel@0 {
status = "okay";
compatible = "simple-panel-dsi";
reg = <0>;
power-supply = <&vcc3v3_lcd>;
backlight = <&backlight>;
reset-gpios = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>;
id-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>;
prepare-delay-ms = <120>;
reset-delay-ms = <120>;
init-delay-ms = <120>;
enable-delay-ms = <120>;
disable-delay-ms = <120>;
unprepare-delay-ms = <120>;
width-mm = <72>;
height-mm = <70>;
dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
MIPI_DSI_MODE_LPM)>;
dsi,format = <MIPI_DSI_FMT_RGB888>;
dsi,lanes = <4>;
panel-init-sequence = [
15 00 02 e0 00
15 00 02 e1 93
15 00 02 e2 65
15 00 02 e3 f8
15 00 02 80 03
15 00 02 e0 01
15 00 02 00 00
15 00 02 01 a9
15 00 02 03 10
15 00 02 04 a9
15 00 02 0c 74
15 00 02 17 00
15 00 02 18 d7
15 00 02 19 00
15 00 02 1a 00
15 00 02 1b d7
15 00 02 1c 00
15 00 02 35 26
15 00 02 37 09
15 00 02 38 04
15 00 02 39 08
15 00 02 3a 0a
15 00 02 3c 78
15 00 02 3d ff
15 00 02 3e ff
15 00 02 3f ff
15 00 02 40 71
15 00 02 41 a6
15 00 02 42 5f
15 00 02 43 ff
15 00 02 44 08
15 00 02 45 01
15 00 02 4b 04
15 00 02 4e 0d
15 00 02 4f 3e
15 00 02 50 01
15 00 02 55 0c
15 00 02 56 01
15 00 02 57 69
15 00 02 58 0a
15 00 02 59 0a
15 00 02 5a 28
15 00 02 5b 15
15 00 02 5d 7f
15 00 02 5e 66
15 00 02 5f 56
15 00 02 60 4a
15 00 02 61 45
15 00 02 62 38
15 00 02 63 3f
15 00 02 64 2c
15 00 02 65 46
15 00 02 66 44
15 00 02 67 3e
15 00 02 68 4d
15 00 02 69 2d
15 00 02 6a 27
15 00 02 6b 18
15 00 02 6c 1b
15 00 02 6d 12
15 00 02 6e 0d
15 00 02 6f 06
15 00 02 70 7f
15 00 02 71 66
15 00 02 72 56
15 00 02 73 4a
15 00 02 74 45
15 00 02 75 38
15 00 02 76 3f
15 00 02 77 2c
15 00 02 78 46
15 00 02 79 44
15 00 02 7a 3e
15 00 02 7b 4d
15 00 02 7c 2d
15 00 02 7d 27
15 00 02 7e 18
15 00 02 7f 1b
15 00 02 80 12
15 00 02 81 0d
15 00 02 82 06
15 00 02 e0 02
15 00 02 00 5f
15 00 02 01 5f
15 00 02 02 53
15 00 02 03 51
15 00 02 04 45
15 00 02 05 47
15 00 02 06 49
15 00 02 07 4b
15 00 02 08 41
15 00 02 09 55
15 00 02 0a 55
15 00 02 0b 55
15 00 02 0c 55
15 00 02 0d 55
15 00 02 0e 55
15 00 02 0f 55
15 00 02 10 55
15 00 02 11 55
15 00 02 12 55
15 00 02 13 55
15 00 02 14 55
15 00 02 15 55
15 00 02 16 5f
15 00 02 17 5f
15 00 02 18 52
15 00 02 19 50
15 00 02 1a 44
15 00 02 1b 46
15 00 02 1c 48
15 00 02 1d 4a
15 00 02 1e 40
15 00 02 1f 55
15 00 02 20 55
15 00 02 21 55
15 00 02 22 55
15 00 02 23 55
15 00 02 24 55
15 00 02 25 55
15 00 02 26 55
15 00 02 27 55
15 00 02 28 55
15 00 02 29 55
15 00 02 2a 55
15 00 02 2b 55
15 00 02 2c 5f
15 00 02 2d 5f
15 00 02 2e 52
15 00 02 2f 40
15 00 02 30 44
15 00 02 31 4a
15 00 02 32 48
15 00 02 33 46
15 00 02 34 50
15 00 02 35 55
15 00 02 36 55
15 00 02 37 55
15 00 02 38 55
15 00 02 39 55
15 00 02 3a 55
15 00 02 3b 55
15 00 02 3c 55
15 00 02 3d 55
15 00 02 3e 55
15 00 02 3f 55
15 00 02 40 55
15 00 02 41 55
15 00 02 42 5f
15 00 02 43 5f
15 00 02 44 53
15 00 02 45 41
15 00 02 46 45
15 00 02 47 4b
15 00 02 48 49
15 00 02 49 47
15 00 02 4a 51
15 00 02 4b 55
15 00 02 4c 55
15 00 02 4d 55
15 00 02 4e 55
15 00 02 4f 55
15 00 02 50 55
15 00 02 51 55
15 00 02 52 55
15 00 02 53 55
15 00 02 54 55
15 00 02 55 55
15 00 02 56 55
15 00 02 57 55
15 00 02 5b 10
15 00 02 5c 02
15 00 02 5d 50
15 00 02 5e 01
15 00 02 5f 02
15 00 02 60 50
15 00 02 61 05
15 00 02 62 06
15 00 02 63 00
15 00 02 64 54
15 00 02 65 55
15 00 02 66 3c
15 00 02 67 73
15 00 02 68 04
15 00 02 69 00
15 00 02 6a 58
15 00 02 6b 04
15 00 02 6c 00
15 00 02 6d 20
15 00 02 e0 00
05 78 01 11
05 05 01 29];
panel-exit-sequence = [
05 00 01 28
05 00 01 10
];
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <67000000>;
hactive = <750>;
vactive = <1334>;
hback-porch = <40>;
hfront-porch = <20>;
vback-porch = <8>;
vfront-porch = <12>;
hsync-len = <20>;
vsync-len = <2>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
phandle = <0xaa>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in_dsi: endpoint {
remote-endpoint = <&dsi_out_panel>;
};
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dsi_out_panel: endpoint {
remote-endpoint = <&panel_in_dsi>;
};
};
};
};The crucial part here, apart from all the parameters, is the cross-reference of ports between the &dsi and panel@0 nodes (panel_in_dsi and dsi_out_panel). I spent a few days figuring out why it didn’t work. This connection forms the final link between the Encoder and the Connector/Panel, completing our chain.
The last thing that’s left is brightness control. It’s done through the backlight node and uses PWM pin:
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 25000 0>;
brightness-levels = <
0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23
24 25 26 27 28 29 30 31
32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71
72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87
88 89 90 91 92 93 94 95
96 97 98 99 100 101 102 103
104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119
120 121 122 123 124 125 126 127
128 129 130 131 132 133 134 135
136 137 138 139 140 141 142 143
144 145 146 147 148 149 150 151
152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167
168 169 170 171 172 173 174 175
176 177 178 179 180 181 182 183
184 185 186 187 188 189 190 191
192 193 194 195 196 197 198 199
200 201 202 203 204 205 206 207
208 209 210 211 212 213 214 215
216 217 218 219 220 221 222 223
224 225 226 227 228 229 230 231
232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255>;
default-brightness-level = <200>;
};Lets build and download our firmware with the a new .dts and check the result:
In the video above, we see the boot process showing the U-Boot logo, the kernel logo, and then finally loading into the Weston desktop. Of course, the touchscreen doesn’t work yet, as we haven’t configured it. So, that will be our next goal! Stay tuned.
![Sonoff NSPanel Pro 120: WiFi/BT [Part 2]](/content/images/size/w600/2025/03/2020-01-23_12-00-02-3.jpg)
![Sonoff NSPanel Pro 120: WiFi/BT [Part 1]](/content/images/size/w600/2025/03/H1b02010384ca42ae9e22684408c56e89Q.jpg)
